New Low Power Run and Low Power Wait Modes. What’s new about them?

Hi, folks,

If you are one of our microcontroller customers, hopefully by now you have heard about our newest MCU family, the Flexis(TM) QE series, which unites our 8-bit S08 MCUs with our new higher-performance 32-bit ColdFire V1 MCUs. We have introduced a few new features on this family intended to help you extend battery life. Two new features I’d like to discuss in detail are the new low power run and low power wait modes.

Issue: the need to run slow
In my first posting, I discussed using the high clock frequencies to reduce average system current by reducing the amount of time spent in higher power run mode and maximizing time spent in the lowest power stop modes. However, this approach may not always be practical. For example, you may need to run a peripheral that doesn’t run in one of the stop modes, such as a timer or UART.

All of our S08 and ColdFire MCUs have on-chip voltage regulators that are active anytime the MCU is in run or wait modes. Therefore the MCUs have a DC offset current that never goes away in these modes. As a result, the slower the operating frequency, the less efficient the MIPs per uA becomes.

Why can’t all peripherals run in stop mode?
There are a couple of reasons many peripherals cannot run in the stop modes. In these modes, the system bus clock is disabled to save power. The peripherals that can run in stop mode either do not require a clock (e.g., analog comparator) or have a built-in clock source (e.g., analog-to-digital converter). The changes to enable the system bus clock in stop modes are non-trivial.

Another reason is that the voltage regulator goes into a low power “loose” regulation mode when one of the stop modes is entered. In this loose regulation state, the regulator can only supply enough current to power a few modules. The current required to run all modules would drain the regulator causing voltage drops that could fall below the minimum operating voltage.

Solution: low power run and wait modes
To resolve these issues, our designers created a new voltage regulator that can provide enough current in its loose regulation mode to power all peripherals at a limited frequency. However, we still had the issue with the bus clock being off in stop modes.

Instead of redesigning our clock architecture to allow the bus clock to run in stop modes, we decided to create two new modes: low power run and low power wait. As you might guess from the names, these modes are simply the standard run and wait modes with the voltage regulator in loose regulation. By taking this approach, we are able to offer full functionality of our peripherals in a very low power state. In addition, the low power run mode allows code execution at a much more efficient MIPs per uA at low frequencies.

Using low power run and wait modes
Using the new low power modes requires configuring just a couple of modules: the clock source (ICS on the QE family) and the low voltage detect (LVD). The clock source must be configured to be running off of an external clock or the crystal oscillator. The reason for this is that the internal clock sources for the S08 and V1 MCUs require a current source that needs the regulator to be in full regulation mode. Therefore, the internal clocks must be disabled. Also, the CPU clock frequency must be limited to 250 kHz to ensure that the regulator is not overloaded if all modules were to be enabled.

The LVD module must also be disabled to enter the low power modes since it requires a bandgap voltage reference that is only available when the regulator is in full regulation. Now we did pull a little trick here. The LVD module can either be disabled by clearing the LVD enable bit (LVDE) or the module can be enabled as long as the LVD stop enable bit (LVDSE) is clear. In this second case, when the MCU is in standard run or wait modes, the LVD is active. When low power run or wait is entered, the LVD will automatically shut down and then restart when the low power mode is exited.

Not a one-off solution
I hope you found this discussion useful and even more importantly, I hope you find these new low power modes useful. These new modes will be standard on our low voltage S08 and ColdFire V1 MCUs moving forward, so it is beneficial for us to make sure our customers are aware of them and understand how the modes can benefit your low power applications.

-Scott

Holistic Approach to Energy Efficient Products

This posting will be an initial discussion on creating energy efficient products. There is no silver bullet for energy reduction meaning that you can’t attack the power problem on a single front. Power is distributed and should be optimized at all levels of the system for the system to be energy efficient. The teams in Freescale are working in multiple areas to enable low power products. These areas are highlighted in the Freescale Energy Efficiency Target

Figure 1: Freescale Energy Efficiency Target.

Process Technology

At the lowest level, the process technology is the foundation of integrated circuits. As the digital process technology continues to scale to smaller dimensions, the leakage current is increasing exponentially which means leakage is becoming a very big problem for components made in deep sub-micron CMOS technologies.

Packaging

Packaging and PCB design can detrimentally impact product power due to the large parasitic capacitances, inductances, and impedances that the circuit IOs must drive to transfer information between components.

Circuit and Module Design

For power reduction in circuit and module designs, we target both active and static power savings. In order to reduce active power, we use techniques such as clock gating or dynamic voltage and frequency scaling in our products. In order to reduce static power, we reduce the voltage or use some form of power gating on high leakage modules. These techniques have trade-offs and many require software to enable these techniques in a platform.

Component Design

The architecture and implementation of components such as microprocessors, application processors, baseband processors, power management ICs, and RF components will dictate the power of the component. We work hard to ensure that only modules to enable the required use cases are used at the lowest frequencies to meet the performance targets.

Platform Design

Platforms are made up of components and software to form an end product. The components you select and how you connect them up for a final product can have a significant impact to the system power.

System and Application Software

Software plays a key role in power consumption. Energy in your system can be squandered away if your software does not take advantage of all power reduction techniques implemented within the hardware.

Tools and Modeling

Tools and modeling are key to understanding where the power is being consumed in a system. This understanding allows us to identify areas in the hardware and software to optimize and to design out the power of the system.

In future posts, I will discuss each area in more detail and provide example techniques that can be employed to reduce power of the overall system. Please let me know if there are any specific topics regarding low power that is of interest and that I may address in a future post.

- Chris

Clock Management for Low Power Applications

For this posting, I’d like to discuss some tips on conserving power through clock management. Many designers equate low power to slow clock frequencies. However, depending on what the MCU is doing and what low-power modes are available on the MCU, running at top speed can actually save power.

What is clock management?

If the MCU has an efficient low-power mode, then you will save the most power by spending the most time in this mode. So if the CPU needs to execute code before returning to sleep, running at the fastest possible speed to complete code execution and return to low-power mode can burn less current than running constantly at slow speeds.

Example of clock management

Take for example the following scenario, a control panel gets a variable update once every 1 second and it takes 16,000 bus cycles to compute the data to be displayed. Running with a typical 32 kHz crystal and assuming a common divide-by-two bus clock, we have a 16 kHz bus, in which case it takes 1 full second to complete the calculations. Now, if we can run at 10 MHz bus clock, it only takes 1.6 milliseconds to complete the calculations and 999.4 milliseconds can be spent in a low power mode.

Other considerations

Of course, not every task an MCU has to perform will benefit from top speed performance. Let’s say our control panel example has a wireless data link. The time required for the wireless communication may not require an 8 MHz bus rate if the wireless data rate is fairly slow. In this case, to minimize power consumption, we want to run the MCU as slow as possible until the wireless communication is complete.

Flexible clock sources

So ideally, we need an MCU with a flexible clock source. Many MCUs have frequency-locked loops (FLLs) and/or phase-locked loops (PLLs) that support multiple frequencies. These allow you to multiply and divide the bus speed to meet the needs of the task and minimize power consumption. The best examples allow the use of external or internal reference clocks and allow you to switch the FLL/PLL on and off on the fly without the need to reset the device.

Feedback

Since this is the first post, let me know if you found it helpful by adding a comment. Also, let me know what low power topics you’d like to see addressed in future posts.

-Scott